The IIS Chip Gallery

Sbrinz (2009)

by

Thomas Koch, Beat Muheim, Frank K. Gurkaynak

Main Details

Application	Test
Technology	130
Manufacturer	UMC
Type	Test Chip
Package	QFN56
Dimensions	1525μm x 1525μm
Gates	50 kGE
Voltage	1.2 V
Clock	30-600 MHz

Description

Test chip for the Microelectronics Design Center. Contains the following main blocks:

• BOAC pads
  The chip uses the new BOnding over active pads. This increases the core area of a miniasic will by about 30%. This was the test chip to make sure that there were no problems with bonding
• Pad performance measurements
  Sbrinz uses a configuration system that allows each pad to be configured during runtime over a serial interface. Coupled by the normal operation modes this will allow us to determine the speed of 4 types of output pads.
• RAM initialization support
  Sbrinz uses a serial interface that would allow the content of SRAMs configured through an SPI interface. The system is not yet bulletproof but can be used as a building block for a more refined solution later on.
• Performance monitor
  Called 'Pergamon' this unit consists of a 32-bit encryption round followed by a corresponding decryption round. The result would equal the input, which is checked and stored in a register. Data input is supplied by a programmable linear feedback shift register. The output of the current round is stored as the key for the next round. The design has around 7.2K gate equivalents and runs at a speed of 125 MHz. Two units are instantiated, one is in the standard cell core area mixed with the rest of the circuit, and a second one is accessible through prober pads and is isolated from the rest of the circuit.
• Ring Oscillator
  Four ring oscillator structures with independent prober pad access have been designed. The oscillation frequency is 13, 26 and 50 MHz. The 13 MHz version has two versions, one with small prober pads, and one with standard sized (60um) pads.
• PLL test block
  This design is based on the FIR filter that is used in VLSI-I/U5, and has a slow interface, and a fast computing section, whose clock is derived from the PLL. It was designed to work faster than 500 MHz, and will allow us to functionally test the PLL in its four different operating ranges (62.5, 125, 250, 500).

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