The IIS Chip Gallery
LEELOO (1999)
by
| Application | Graphics |
| Technology | 350 |
| Manufacturer | austriamicrosystems |
| Type | Research |
| Package | CQFP208 |
| Dimensions | 7000μm x 7000μm |
| Gates | 700 kGE |
| Voltage | 3.3 V |
| Power | 324 mW, 2.7V |
| Clock | 200 MHz |
Real-time motion pictures providing image quality superior to standard video in terms of resolution and color fidelity are often required. In many applications, e.g. in biomedicine or machine vision, only cameras with a single charge-coupled device (CCD) sensor can satisfy the stringent space requirements. The reconstruction of the RGB image from the CCD with a Bayer color filter array requires an extremely high computation effort if reasonable frame rates and artefact-free interpolation quality is to be achieved.
The LEELOO ASIC performs this task for 1024 by 1024 pixel images at 30 frames per second. The raw image data from the camera head is received by onchip low-voltage differential signaling receivers. Prior to interpolation, this data is processed by a pixelwise black-current and white-gain balancing. The interpolation algorithm is based on complex algorithms over nine CCD lines which are stored on-chip. To achieve best color fidelity with different scene illuminations, a 6x3 matrix transformation is performed on the interpolated RGB data for color space adjustment. Additional highlights of the ASIC are scan conversion for a PAL video encoder and two-dimensional focus criterion calculation on a sizable window. Two synchronous DRAM controllers enable cost-efficient intermediate data storage and the hardwareassisted parallel interface provides easy configuration access to all units.