The IIS Chip Gallery
MAIN (1990)
Additional pictures below, click to see larger versions
by
| Application | Cryptography |
| Technology | 1500 |
| Manufacturer | VLSI Tech |
| Type | Semester Thesis |
| Package | DIP64 |
| Dimensions | 2930μm x 4670μm |
| Gates | 9 kGE |
| Voltage | 5 V |
| Clock | 20 MHz |
MAIN (Modular Arithmetic INverter) is a hardware implementation of a 16-bit number modulo (2^16+1). It uses an algorithm suggested by J. Gordon, and implements multiplications and divisions as a series of add and shift operations.
MAIN has a 4-stage pipeline and can perform 2 inversions simultaneously. One inversion will be finished in at most 80 cycles, therefore the chip is able to invert 500'000 numbers per second.
The inversion circuit implemented here was re-used in later chips implementing cryptographic modules.