The IIS Chip Gallery
Chronos2 (2021)
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| Application | Low-power |
| Technology | 65 |
| Manufacturer | TSMC |
| Type | Research |
| Package | Baredie |
| Dimensions | 1000μm x 1175μm |
| Voltage | 1.2 V |
| Power | 6 mw @1.2V 25C |
| Clock | 64 MHz |
The IC realizes a Bluetooth Low Energy Transmitter with GMSK-Modulator, DPLL and TX output driver. The DPLL is a fractional low-power PLL with integrated 2-point modulation. It uses a Class C DCO, an analog, differential ramp based phase detector and a digital loop filter. Two different TX output drivers have been implemented: a switched-capacitor based PA and a version with a bootstrapped switch which uses an input voltage that is generated from a buck DCDC-converter.
The PLL consumes only 700 microWatt, and the whole chip 6mW when transmitting at 4dBm output power.
This is a re-run of the earlier Chronos chip with some corrections.