The IIS Chip Gallery

Vivosoc (2015)

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by

Giovanni Rovere, Florian Glaser, Xu Han, Schekeb Fateh

Main Details

Application	Processor
Technology	130
Manufacturer	SMIC
Type	Research
Package	Baredie
Dimensions	4000μm x 3200μm
Gates	600 kGE
Voltage	1.2 V
Power	45 mW (@40MHz, 1.2V)
Clock	140 MHz

Description

The VivoSoC is a chip the combines a very flexible analog acquisition circuitry and SAR-ADC with a Parallel Ultra Low Power processor (PULP) This is meant to be used for biomedical signal acquisition, such as EEG, ECG and EMG in a wearable context. The Analog Front End (AFE) design is based on the chip CerebroV4.1 Jack while the processor is based on PULP v2 design with the addition of a peripheral block that configures and reads out data from the AFE.

Main chip features:

• 8-channels signal conditioning with selectable gain and Electrode Impedance Measurement
• Fully flexible 13ENOB SAR-ADC with on chip calibration and reference buffers.
• Dual core Parallel Ultra Low Power processor (PULP).
• 2 Master SPI, 1 Slave SPI, ports 8 GPIO pins, UART.
• Three dependent clock domains: Processor Cores, Processor Peripherals and AFE.
• Two independent power domains for the Digital Processor and for the AFE.

The name VivoSoC is based on the Italian word "Vivo" that can be translated as "Alive".

A newer version of this chip is VivoSoc2

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